The present invention relates generally to computer arrays, and more particularly to an improved system for implementing a column redundancy scheme for arrays with controls that span multiple data bits.
The ability to provide a work around for errors discovered during the testing of integrated circuits can result in fewer integrated circuits being scrapped due to a single faulty data bit. The cost of adding memory and circuitry to every integrated circuit is balanced against the cost of scrapping an entire integrated circuit because of a faulty data bit. The cost of added circuitry may be relatively minor when dealing with control signals that are contained in a single data bit because only one redundant data bit may be required to provide a backup storage location. However, the cost of added circuitry increases with control signals that span more than one data bit. The data bits spanned by a control signal, referred to as a field, require that an extra or redundant field be added to the circuitry to provide a backup storage location. As the size of the field increases, the cost of the added circuitry increases.
An example of a control signal that could span multiple data bits is the byte write (xe2x80x9cBWxe2x80x9d) control signal that may be associated with Static Random Access Memory (SRAM). Using an example where the BW control signal field length is four, providing a backup storage location would require that a redundant field containing four data bits be added to the circuitry on the integrated circuit. If an error is detected in one of the four data bits in a data field specified by the BW control signal during testing of the integrated circuit, entire fields would be shifted to correct for the defective data bit. This steering is implemented for both input and output signals in order to bypass a defective bit. Typically, this occurs by shifting fields to prior fields and by shifting the first field to the redundant field. The fields stored after the failing data bit are not shifted. For example, if an array contains six fields and field four contains a faulty data bit, then field one would be moved into the redundant field, field two into field one, field three into field two, and field four into field three. Fields five and six would remain unaffected. The shifting occurs by changing the input to the field selection multiplexors on the integrated circuit.
Providing a redundant data field for error recovery during system test can require significant overhead in terms of space for extra circuitry. The amount of overhead varies based on the field length. In addition, the fields must be the same length so that they can be shifted when an error is detected.
An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit. The system also includes programmable logic in communication with the field control signal multiplexor, the spare control signal multiplexor, the data multiplexor and the spare data multiplexor to cause the steer around to take place in response to detecting a defective data bit in the array.